This invention relates generally to a trench DRAM memory cell and more specifically to a process method for providing process window enhancement to protect the DT (deep trench) top structure of a vertical gate transistor during subsequent processing of the AA (active area).
The primary driving motivator in commercial memory cells and architecture is the desire to pack more memory capability into a smaller integrated circuit. This goal necessarily involves competing trade-offs in cost, circuit complexity, power dissipation, yield, performance, and the like. Trench capacitors are known in the art as an architecture whereby the overall size (in terms of surface area or chip xe2x80x9creal estatexe2x80x9d) of the memory cell is reduced. The size reduction is accomplished by forming the capacitor of the memory cell in a trench.
As is known in the art, a typical DRAM cell includes a capacitor upon which is stored a charge (or no charge depending upon the cell""s state) and a pass transistor, which is used to charge the capacitor during writing and in the read process to pass the charge on the capacitor to a sense amplifier. In most recent manufacturing, planar transistors are used for the pass transistors. Such planar transistors have a critical dimension of gate length that is typically 110 nm or greater. Below that size, the transistor performance becomes degraded and is very sensitive to process tolerances. As such, for DRAM cells that are desired to be shrunk below a roughly 110 nm ground rule, existing planar transistors cannot provide the performance necessary for proper DRAM cell operation. A need exists, therefore, for a DRAM memory cell employing a pass transistor architecture that maintains acceptable performance even when shrunk to very small dimensions. Deep trench memory cells combined with a vertical pass transistor represent one approach to meet this challenge.
A method of manufacturing deep trench memory cell comprises: forming a buried plate within a semiconductor substrate, forming a deep trench having sidewalls within an active area of a semiconductor substrate, forming a trench collar oxide along the sidewalls of the deep trench. The method further comprises filling the trench with polysilicon. After subsequently etching the poly in the trench, the method further comprises etching the trench collar which leaves a divot and then filing the divot with polysilicon A trench top oxide is then formed on the trench and divot polysilicon, filling the trench with a gate polysilicon above the trench top oxide, forming a first doped region adjacent one sidewall of the trench and a second doped region adjacent another sidewall of the trench. These steps are followed by forming a contact to the gate polysilicon and connecting the gate polysilicon to a word line, and forming a contact to the first and second doped regions and connecting the first and second doped regions to a bit line.
The method also provides for forming the capacitor of the memory circuit being formed in a lower portion of a trench, and further comprises a logical pass transistor having a vertical gate formed within an upper portion of the trench, along with a source region, a drain region, and a gate with a gate oxide adjacent the source and drain regions.
As will be appreciated, one problem area in the manufacturing process is protecting a nitride spacer from damage that often results during processing steps such as stripping of the pad nitride layer. Therefore, it would be advantageous to provide a simple and efficient method of xe2x80x9cenhancing the process windowxe2x80x9d by protecting the nitride spacer.
Enhancement of the process window and protection of the nitride spacer, according to the present invention, is achieved in a process for manufacturing deep trench memory cells in a substrate covered by a pad nitride layer, which in turn is covered by an oxide layer. The deep trench memory cell also includes a polysilicon gate (or sometimes referred to as a poly gate) that fills the trench to a level below the bottom surface of the pad nitride layer. Further according to the process steps, a nitride layer is formed over the layer of oxide and the side walls of the trench down to the top surface of the gate poly. The nitride layer is then etched to form a nitride spacer that has a top shoulder which is spaced less than about 40-50 nm below the top surface of the pad nitride layer. The spacer also extends down to the top surface of the gate poly so as to define an aperture surrounded by the nitride spacer. The aperture is then filled with a poly stud that extends from the gate poly to a level just slightly below the top surface of the pad nitride layer. A nitride liner is then formed over the poly stud.